1. Field of the Invention
The present invention relates to a programmable device which can be programmed electrically, and more particularly to a programmable device suitable for construction of a semiconductor integrated circuit. And the present invention relates to a method of fabricating such a programmable device.
2. Description of the Prior Art
A programmable read-only-memory (PROM) to which data can be electrically written by the user is extensively used as a semiconductor memory because it can readily provide a read-only-memory (ROM) which contains information (data). For this reason, a programmable logic device (PLD) to which the user can write the desired functions is also used as a logic circuit.
Such PROMs and PLDs consist of small programmable devices which information can be electrically written to, and can store the information even after power is cut off. An example of the prior art programmable device is disclosed in Japanese Laid-Open Patent Publication No. 62-242336.
FIG. 7 shows a planar structure of a prior art programmable device. As shown in FIG. 7, a field insulating film 3 is selectively formed over an isolation region in the main surface of a p-type silicon substrate 1. In the surface region of the silicon substrate 1 over which the field insulating film 3 is not formed, there is formed an n.sup.+ -diffusion layer that constitutes a lower electrode 2. Also formed on the silicon substrate 1, with the field insulating film 3 interposed therebetween, is an upper electrode 5 formed from a polycrystalline silicon film. The upper electrode 5 is disposed intersecting at right angles with the lower electrode 2. The region (indicated by oblique hatching in FIG. 7) where the lower electrode 2 and the upper electrode 5 overlap each other is a program region 6 of the programmable device. A PROM or a PLD is a circuit consisting of a large number of such programmable devices which are integrated on a single silicon substrate.
FIG. 8 is a cross sectional view taken along line C--C in FIG. 7. As shown in FIG. 8, the upper surface of the lower electrode 2 is covered with a thin program insulating film 7 on top of which the upper electrode 5 is formed. FIG. 9 is a cross sectional view taken along line D--D in FIG. 7. As shown in FIG. 9, while the upper surface of the lower electrode 2 is covered with the program insulating film 7, the surface regions of the silicon substrate 1 where the lower electrode 2 is not formed, are covered with the field insulating film 3. That is, the entire upper surface (main surface) of the silicon substrate 1 is covered with the program insulating film 7 and the field insulating film 3. Thus, the upper electrode 5 is electrically isolated from the silicon substrate 1 by the program insulating film 7 and the field insulating film 3.
In the above programmable device of the prior art, programming, i.e. writing, is performed by applying between the upper electrode 5 and the lower electrode 2 a voltage that is sufficiently higher than the withstanding voltage of the program insulating film 7 and is therefore strong enough to break down the program insulating film 7, thereby accomplishing electrical conduction between the upper electrode 5 and the lower electrode 2.
In the above programmable device, the area of the program region 6 is determined by the respective widths of the upper electrode 5 and the lower electrode 2 as shown in FIG. 7. Because of the need to reduce the wiring resistance, the widths of the upper electrode 5 and the lower electrode 2 cannot be substantially reduced, and generally take two to three times the minimum feature size, which, as a result, prevents the area of the program region 6 from being substantially reduced. In an actual semiconductor integrated circuit (e.g., PROM or PLD), since there are thousands, or tens of thousands of program regions 6, the capacitance, as a whole of unwritten program regions 6, results in a substantially great parasitic capacitance in the semiconductor integrated circuit.
Furthermore, in the above programmable device of the prior art, since the lower electrode 2 is a heavily doped region formed in the semiconductor substrate 1, a large parasitic capacitance is formed between the semiconductor substrate 1 and the lower electrode 2 According to recent semiconductor integrated circuit technology, since the thickness (junction depth) of the heavily doped region constituting the lower electrode 2 is usually thinner (shallower) than 0.3 .mu.m, the lower electrode 2 is inevitably provided with a high sheet resistance of 40 to 50 .OMEGA./.quadrature..
Thus, the prior art programmable device has the shortcoming of reducing the operating speed of a semiconductor integrated circuit formed from such devices.
In semiconductor integrated circuits having such programmable devices, polycrystalline silicon is widely used as the material of the electrode (upper electrode 5) because of such advantages as resistance to high temperature heat treatment and excellent adhesion to the surface insulating film. Usually, the electrode in such semiconductor integrated circuits also functions as a line interconnecting between the electrodes of individual programmable devices integrated on the same semiconductor substrate. Therefore, in this specification, the electrode and the line are collectively referred to as the "electrode".
Since a lower resistance is desirable for the electrode, when a polycrystalline silicon film is used to form the electrode, dopant impurities must be added (diffused) into the polycrystalline silicon layer to reduce the resistance thereof. Also, when, for example, an electrode having a laminated structure (polycide structure) comprising a polycrystalline silicon layer and a metal silicide layer is used instead of the above described electrode, dopant impurities are often diffused into the electrode for such purposes as stabilizing the threshold voltage of MISFETs integrated on the same semiconductor substrate as the programmable devices.
A prior art method of diffusing dopant impurities into the electrodes in a semiconductor circuit is described below, with reference to FIGS. 12A to 12D. First, as shown in FIG. 12A, a field oxide film 102 is selectively formed over an isolation region of the main surface of a p-type silicon substrate 101, so that a plurality of regions over which the field oxide film 102 is not formed, are electrically isolated from each other by the field oxide film 102. Next, program insulating films 103 are formed over each of the regions of the silicon substrate 101 over which the field oxide film 102 is not formed. Usually, the thickness of the program insulating films 103 formed over device regions 104 of the silicon substrate 101 is approximately the same as that of the program insulating films 103 formed over scribe line regions 105 thereof.
Next, as shown in FIG. 12B, a polycrystalline silicon film -06 is grown over the program insulating films 103 and the field oxide film 102. Further, as shown in FIG. 12C, arsenic ions of about 1 .times. 10.sup.16 /cm.sup.2 are implanted into the polycrystalline silicon film 106 by an ion implantation method.
Thereafter, as shown in FIG. 12D, the polycrystalline silicon film 106 is patterned with a desired geometry by a photoetching technique to form upper electrodes 107.
According to the above fabrication method of the prior art, electrical charges are stored in the polycrystalline silicon film 106 by the implanted ions during the ion implantation process, and the charges are discharged into the substrate 101 through the program insulating films 103 which are thinner than the field oxide film 102. Since the program insulating films 103 are formed to approximately the same thickness regardless of the places where they are formed, the discharge current of the same density flows in any region. This may cause the program insulating films 103 in the device regions 104 to break down, or if not break down, may suffer deterioration in their dielectric strength as a result of injection of the electric charges. Interface levels may also be formed at the interfaces between the program insulating films 103 and the silicon substrate 101. The resulting problem is a drop in reliability of the device having the program insulating films 103.